Mindspeed enables high-density 100 Gigabit Ethernet systems with lowest-power 28G clock and data recovery technology

OFC/NFOEC 2012, NEWPORT BEACH, USA: Mindspeed Technologies Inc. announced the industry’s lowest-power clock and data recovery (CDR) capable of supporting data rates from 25 to 28 gigabits per second (Gbps). The low power dissipation is a critical requirement for enabling the 100 Gigabit Ethernet (100GbE) system port densities that the industry must achieve in order to handle increasing internet traffic and escalating online video content demand.

Mindspeed will be demonstrating its new CDR technology at the The Optical Fiber Communication Conference and Exposition and the National Fiber Optic Engineers Conference (OFC/NFOEC 2012), from March 6-8, 2012, in booth #1761/173 at the Los Angeles Convention Center. The company will also be showcasing its broad range of physical media devices (PMDs) for equipment used to deliver fiber-to-the-x (FTTx) multi-play services via fiber-access networks.

“Increasing internet traffic and the demand for online video content is driving the need to upgrade network connections from 10Gbps to 100Gbps,” said Hasnain Bajwa, senior VP and GM, high-performance analog (HPA), Mindspeed. “To enable this upgrade, CDR integrated circuits (ICs) are required that can reset the link’s jitter budget at data rates from 25Gbps to 28Gbps. These CDRs also must dissipate extremely low power in order to achieve high 100Gbps system port densities. Mindspeed’s 28Gbps CDR dissipates the lowest power in the industry, and will be a key building block for next-generation networking systems.”

Mindspeed’s CDR can support data rates required for multiple standards including 100GbE, Infiniband Enhanced Data Rate (EDR), 32G Fibre Channel and Optical Transport Network (OTU4). The low-power solution will enable next-generation optical and copper module form factors such as C Form-factor Pluggable2 (CFP2) and Quad Small Form-Factor Pluggable Plus (QSFP+). Mindspeed’s CDR IC also integrates such key features as an input equalizer and output de-emphasis to optimize the link performance. It also is reference-free, reducing the number of components required to implement this solution. Further, it achieves very high input sensitivity, removing the need for including a discrete limiting amplifier in the module.