MHEG-5 is an open standard middleware solution, an application program interface (API), designed specifically for low-cost memory constrained devices -- particularly suitable for digital interactive TV (iTV) services and is platform agnostic. Simply put, MHEG-5 is a simple object-orientated programming language.
MHEG-5 was initially adopted in 1998 by ONDigital in the United Kingdom (rebranded as ITV Digital) for use in the world’s first pay-TV digital terrestrial television (DTT) network. ONDigital lead the industry wide specification and development task of the first MHEG-5 profile, which subsequently (after the collapse of ITVDigital) formed the basis for deployment of interactive services on the UK DTT platform (Freeview).
Developed by the ISO-MHEG group and DAVIC in 1995, it is intended as a UI for DAVIC interactive services and VOD. MHEG-5 has been standardized in ISO 13522-5 and adopted by the UK DTG in 1997.
Going by its history on IMPALA (The International MHEG Promotion Alliance), MHEG (Multimedia and Hypermedia information coding Expert Group) originally developed and standardized by Working Group 12 (WG12) of the ISO -- officially known as ISO/IEC JTC1/SC29/WG12. It was developed in the mid 1990s as part of the DAVIC (Digital Audio Video Council) standardization effort to support interactivity and navigation of multimedia services on various small footprint devices.
WG12 issued a suite of documents (MHEG parts 1-8) as part of MHEG standard covering extensions for scripting language (MHEG-6), testing and interoperability (MHEG-7) and support for encodings in XML format (MHEG-8). Part 5 of the standard, officially known an ISO/IEC 13522-5, or more commonly know as MHEG-5 that is of primary relevance to interactive DTV.
So what's hot about MHEG-5? Well, the standard's profile evolved to UK Profile 1.06 (current); ETSI standard ES 202184. And now, new international profiles extend the UK profile. These include: New Zealand -- extra Maori characters and EPG key; Hong Kong -- Traditional Chinese font; Singapore/China - simplified Chinese font. Certain other extensions are said to be under development within DTG for possible deployment in 2008. These include IP interaction channel (return path), improved graphics, HD compatibility and support, and PVR support.
Heading for India?
What's more significant is that MHEG-5 is said to be launching in India and in Hong Kong in 2008! Trials and evaluations are reportedly ongoing in Ireland, Malaysia, Singapore, Turkey, India and Russia. There is said to be interest from other countries in Europe and Asia as well.
MHEG-5 has no known essential IPR. The MHEG middleware software is typically less than US$1 per receiver. It has had wide integration into iDTVs in Europe. Finally, MHEG is proposed as the UI for new Common Interface spec (CI+), as well.
I hope to be speaking with IMPALA sometime soon about its plans for India and update you appropriately!
Thursday, March 27, 2008
Saturday, March 15, 2008
NXP India achieves RF CMOS in single chip
NXP Semiconductors India has developed the PNX4902, an ultra low-cost GSM/GPRS single chip, which was announced this February. The highlight -- the entire analog and RF work done has been in Bangalore! You might wonder what's so unique about this!
Well, let's start with what is tough about RF CMOS in single chip! CMOS is primarily a digital process. The analog circuit design in CMOS is tough, and the RF circuit design in CMOS is even tougher. Now, the co-existence of RF CMOS circuits with noisy digital in a single chip was (and is) considered the holy grail of chip design.
Next, cellular standards (such as GSM, EDGE) and specs are much tougher than other comparable standards like FM, Bluetooth, etc. Also, some key cellular parameters like RX sensitivity become tougher for single chips aimed at emerging markets. Especially, we all know that base stations are sparse in rural areas. Taking all of these as a whole -- RF design in presence of digital noise is the biggest challenge in a single chip!
Factors enabling single chip design
There are said to be three factors. One, RF CMOS is the high quality analog/RF design in CMOS. The high-performance RF blocks like LNA, mixers, etc., used to be the domain of BiCMOS, a higher cost technology. Next, fine-line CMOS (0.18mm and lower) provide high fT and lower noise.
Two, there are new architectures that minimize analog signal processing. Chip designers to convert the analog signal to digital -- so they might as well do it early -- analog-to-digital conversion at the IF, instead of at DC. There's also a need to move the final down-conversion and filtering into digital domain.
Three, the use of DSP to calibrate the analog performance. Things like temperature and process sensitivities in analog circuits need adjustments. Also, the digital engines can provide the ability to 'lock-in' the performance. Finally, a strong 'engineering culture' is a MUST to execute on complex chips.
Factors enabling AeroFone single chip design
NXP had acquired Silicon Labs Wireless group in 2007. Silicon Labs was a leader in RF CMOS, and so it also acquired numerous patents and trade secrets. Trade secrets for integration of RF CMOS circuits with noisy digital provide an edge over competitors as the integration intensifies.
Thereafter, NXP went on to form the NXP India single-chip design team. As single chip products are designed for emerging economies, NXP India invested heavily to develop the design expertise in Bangalore. The seed group of chip leads and system leads relocated from USA to India to start an analog/RF competency center for developing highly integrated chips.
The NXP India single chip design team has the vision to be the best center of competence in architecture and design of highly integrated circuits (ICs) for emerging market products. It is building the best analog/RF group in India.
Well, let's start with what is tough about RF CMOS in single chip! CMOS is primarily a digital process. The analog circuit design in CMOS is tough, and the RF circuit design in CMOS is even tougher. Now, the co-existence of RF CMOS circuits with noisy digital in a single chip was (and is) considered the holy grail of chip design.
Next, cellular standards (such as GSM, EDGE) and specs are much tougher than other comparable standards like FM, Bluetooth, etc. Also, some key cellular parameters like RX sensitivity become tougher for single chips aimed at emerging markets. Especially, we all know that base stations are sparse in rural areas. Taking all of these as a whole -- RF design in presence of digital noise is the biggest challenge in a single chip!
Factors enabling single chip design
There are said to be three factors. One, RF CMOS is the high quality analog/RF design in CMOS. The high-performance RF blocks like LNA, mixers, etc., used to be the domain of BiCMOS, a higher cost technology. Next, fine-line CMOS (0.18mm and lower) provide high fT and lower noise.
Two, there are new architectures that minimize analog signal processing. Chip designers to convert the analog signal to digital -- so they might as well do it early -- analog-to-digital conversion at the IF, instead of at DC. There's also a need to move the final down-conversion and filtering into digital domain.
Three, the use of DSP to calibrate the analog performance. Things like temperature and process sensitivities in analog circuits need adjustments. Also, the digital engines can provide the ability to 'lock-in' the performance. Finally, a strong 'engineering culture' is a MUST to execute on complex chips.
Factors enabling AeroFone single chip design
NXP had acquired Silicon Labs Wireless group in 2007. Silicon Labs was a leader in RF CMOS, and so it also acquired numerous patents and trade secrets. Trade secrets for integration of RF CMOS circuits with noisy digital provide an edge over competitors as the integration intensifies.
Thereafter, NXP went on to form the NXP India single-chip design team. As single chip products are designed for emerging economies, NXP India invested heavily to develop the design expertise in Bangalore. The seed group of chip leads and system leads relocated from USA to India to start an analog/RF competency center for developing highly integrated chips.
The NXP India single chip design team has the vision to be the best center of competence in architecture and design of highly integrated circuits (ICs) for emerging market products. It is building the best analog/RF group in India.
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